21C3 Fahrplan Version 1.1.7
21st Chaos Communication Congress
Vorträge und Workshops
| Referenten | |
|---|---|
 |
Klaus Schleisiek |
| Fahrplan | |
|---|---|
| Tag | 1 |
| Ort | Saal 4 |
| Beginn | 21:00 Uhr |
| Dauer | 01:00 |
| INFO | |
| ID | 42 |
| Art | Vortrag |
| Themenbereich | Hacking |
| Sprache | englisch |
| FEEDBACK | |
|---|---|
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Cored Programming
Building systems on your own soft core
A presentation of the public-domain "uCore" written in VHDL that can be used by the "Core Aided Programmer" to realise systems in FPGAs. Its architecture, its hardware/software co-design approach, its prototyping board and its software development environment.
Systems on a Chip, initially reserved to the ASIC community and big money, can now be carried out on an FPGA basis by small enterprises. Processor kernels programmed in VHDL or Verilog meet the operating system interface programmed in C. The "Core Aided Programmer" is able to tune the hardware/software interface towards simplicity, understandability and energy efficiency without having to struggle with (un)known bugs.
"uCore" is a processor kernel based on Forth. It has a data and a return stack and separate program and data memories. Its transputerish "prefix" code structure makes the data word width independent from its 8 bit code width and therefore, its data width can be set by one VHDL constant, and it can be interrupted after each instruction. Because of its stacks, no registers need to be saved on interrupts. It has an innovative exception mechanism, which makes API code easier to read and therefore, more reliable.
A 32-bit instantiation fits into 1/3 of the by now "small" XC2S200 (Xilinx) or EP1C6 (Altera).